The present invention relates to a semiconductor storage device that writes or erases data by applying high voltage to a floating gate. More specifically, the present invention relates to a technology for prevention against damage due to a reset during operations of the device.
The flash memory, one of the nonvolatile memory, is electrically rewritable nonvolatile memory and is also termed EEPROM. The flash memory uses a field effect transistor as a memory cell. The field effect transistor has a floating gate. The flash memory applies high voltage to a selected memory cell. The flash memory stores an electric charge in the floating gate or discharges the stored electric charge to rewrite the stored contents.
The flash memory comprises a memory cell array, a voltage converter, a timer circuit, a discharge circuit, a sensor circuit, a word line decoder, and a control circuit. The memory cell array comprises memory cells that store data and are disposed in a matrix. The voltage converter generates high voltage needed to rewrite the stored contents. The timer circuit determines the timing to terminate the rewriting. The discharge circuit discharges the high voltage after termination of the rewriting. The sensor circuit detects that the high voltage is discharged. The word line decoder selects a word line based on an address signal and outputs high voltage when rewriting data. The control circuit controls overall operations of these circuits.
When the flash memory is in the standby state, i.e., neither reading nor writing is performed, the voltage converter does not operate. The voltage converter outputs a normal power supply voltage. The word line decoder stops operating. A reference potential (ground potential) is output to all word lines.
When an erase command is supplied to the flash memory's control circuit, for example, the control circuit outputs an erase start signal to start an erase operation. The erase start signal is supplied to the voltage converter, the timer circuit, the discharge circuit, and the word line decoder to release the standby state of these circuits. When the voltage converter outputs a boosted voltage (power supply voltage at this time), the word line decoder outputs this voltage to a word line selected based on the address signal.
After a specified lapse of time, the control circuit supplies an erase execution signal to the voltage converter and the timer circuit. This allows the voltage converter to start a boost operation. An output boosted voltage increases up to a specified high voltage (erase voltage) with the lapse of time. In addition, the timer circuit starts time monitoring to determine the timing to terminate the erase operation.
Let us assume that the boosted voltage output from the voltage converter rises up to the erase voltage and another specified time elapses. Then, the word line supplies the erase voltage to erase the stored contents in the memory cell connected to the selected word line.
After the monitoring time of the timer circuit elapses, the timer circuit outputs an erase termination signal to the control circuit. This stops the erase execution signal output from the control circuit. A discharge control signal is output instead. Stopping the erase execution signal stops the boost operation of the voltage converter and the time monitoring of the timer circuit. Since the discharge control signal is output, the discharge circuit starts discharging the electric charge from output wiring of the voltage converter and from the word line decoder. In addition, the sensor circuit starts monitoring the boosted voltage.
After the boosted voltage is discharged and the specified power supply voltage is resumed, the sensor circuit outputs a discharge termination signal to the control circuit. This stops the erase start signal output from the control circuit, placing the voltage converter, the timer circuit, the discharge circuit, and the word line decoder in the standby state.
However, the conventional flash memory is subject to the following problems.
For example, the LSI (large scale integrated circuit) such as a micro-controller integrates not only a CPU (central processing unit), but also memory, an input/output circuit, and the like into a single chip. Specified programs are stored in the memory to perform specified operations. As the memory installed on the micro-controller, the flash memory is used to store programs and permanent data.
The micro-controller may be supplied with a reset signal from the outside. In this case, the micro-controller is configured to reset all the circuits including the CPU irrespectively of operating states at the time of the reset. Accordingly, supplying the reset signal allows the control circuit to immediately stop supplying the erase start signal, the erase execution signal, and the discharge control signal to the flash memory installed on the micro-controller.
If the reset signal is supplied during an erase operation of the flash memory, for example, the standby state immediately takes effect. At this time, the voltage converter is still active. The discharge circuit is inactive. If the high voltage directly changes to the reference potential, there is a possibility of causing dynamic latch-up. The dynamic latch-up condition allows a large current to continuously flow triggered by a current flowing into the reference potential. Further, transistors themselves are subject to the decreased voltage resistance ability because the transistors are miniaturized and the power supply voltage is decreased. When the high voltage directly changes to the reference potential, there has been the problem of damaging a transistor applied with the high voltage.